The cyclic redundancy check (CRC) is extremely efficient and well suited for error detection in transmission, retrieval or storage of variable length records of binary data. CRC is capable of detecting nearly all patterns of error with almost negligent amount of redundancy.
CRC is also very well known. See, for example, "Cyclic Codes for Error Detection", W. W. Peterson and D. T. Brown, Proceedings of the IRE, pages 228 to 235, January, 1961, and "A Multi-channel CRC Register", Arvind M. Patel, Spring Joint Computer Conference, 1971.
A linear feedback register is essentially the only hardware needed for encoding and decoding variable length binary data for error detection by means of a CRC byte. The CRC byte is generated using a GF(2) polynomial divider circuit. In such a circuit, the binary information is serially shifted into a feedback shift register as the information is transmitted. The CRC byte is transmitted at the end of the binary data and received in sequence at the receiver. The generated CRC byte is then compared with the received CRC byte for detection of any errors in the received message which is processed in the same manner by a feedback shift register. The number of digits in the CRC byte determines the checking capability of the code and, in general, equals the number of stages of the encoding and decoding shift register.